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In Stock

RoHS

Mfr.	Mfr. No:	Qty	Ext Total

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AS4C16M32SC-7TIN

Name: Alliance Memory AS4C16M32SC-7TIN
Brand: Alliance Memory
SKU: 913-AS4C16M32SC-7TIN
Price: 23.04 USD
Availability: InStock

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Mouser No:

913-AS4C16M32SC-7TIN

Mfr. No:

AS4C16M32SC-7TIN

Mfr.:

Alliance Memory

Description:

DRAM SDR, 512MB, 16M x 32, 3.3V, 86PIN TSOP II, 133 MHZ, Industrial Temp - Tray

Datasheet:

AS4C16M32SC-7TIN Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about Alliance Memory AS4C16M32SC-7TIN

In Stock: 29

Stock:: 29 Can Dispatch Immediately

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Factory Lead Time:: 16 Weeks Estimated factory production time for quantities greater than shown.

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Unit Price:

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Ext. Price:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$23.04	$23.04
	$21.34	$213.40
	$20.68	$517.00
	$20.17	$1,008.50
	$19.62	$2,118.96
	$18.67	$4,032.72
	$18.26	$9,860.40
1,080	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM
Memory Size:	512 Mbit
Data Bus Width:	32 bit
Maximum Clock Frequency:	133 MHz
Package/Case:	TSOP-II-86
Organisation:	16 M x 32
Access Time:	17 ns
Supply Voltage - Min:	3 V
Supply Voltage - Max:	3.6 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Series:	AS4C16M32SC
Packaging:	Tray
Brand:	Alliance Memory
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	108
Subcategory:	Memory & Data Storage
Supply Current - Max:	70 mA
Unit Weight:	9.245 g

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Filter Document:

Datasheet

AS4C16M32SC-7TIN Datasheet (PDF)

REACH Declaration (PDF)

CNHTS:: 8542329010
USHTS:: 8542320028
TARIC:: 8542323100
ECCN:: EAR99

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.