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In Stock

RoHS

Mfr.	Mfr. No:	Qty	Ext Total

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AS4C2M32SA-6TCN

Name: Alliance Memory AS4C2M32SA-6TCN
Brand: Alliance Memory
SKU: 913-AS4C2M32SA-6TCN
Price: 3.99 USD
Availability: InStock

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Mouser No:

913-AS4C2M32SA-6TCN

Mfr. No:

AS4C2M32SA-6TCN

Mfr.:

Alliance Memory

Description:

DRAM SDRAM, 64MB, 2M X 32, 3.3V, 86PIN, TSOP II, 166MHZ, Commercial Temp - Tray

Datasheet:

AS4C2M32SA-6TCN Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about Alliance Memory AS4C2M32SA-6TCN

In Stock: 58

Stock:: 58 Can Dispatch Immediately

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Factory Lead Time:: 20 Weeks Estimated factory production time for quantities greater than shown.

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Ext. Price:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$3.99	$3.99
	$3.72	$37.20
	$3.62	$90.50
	$3.53	$176.50
	$3.44	$371.52
	$3.31	$714.96
	$3.24	$1,749.60
	$3.17	$3,423.60

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM
Memory Size:	64 Mbit
Data Bus Width:	32 bit
Maximum Clock Frequency:	166 MHz
Package/Case:	TSOP-II-86
Organisation:	2 M x 32
Access Time:	5.4 ns
Supply Voltage - Min:	3 V
Supply Voltage - Max:	3.6 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Series:	AS4C2M32SA
Packaging:	Tray
Brand:	Alliance Memory
Country of Assembly:	TW
Country of Diffusion:	TW
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	108
Subcategory:	Memory & Data Storage
Supply Current - Max:	95 mA

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Filter Document:

Datasheet

AS4C2M32SA-6TCN Datasheet (PDF)

Models

AS4C2M32SA-6TCN Symbol & Footprint by SnapMagic

REACH Declaration (PDF)

CNHTS:: 8542329000
USHTS:: 8542320002
JPHTS:: 854232021
MXHTS:: 8542320201
ECCN:: EAR99

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.