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In Stock

RoHS

Mfr.	Mfr. No:	Qty	Ext Total

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AS4C32M16D1A-5TCN

Name: Alliance Memory AS4C32M16D1A-5TCN
Brand: Alliance Memory
SKU: 913-4C32M16D1A5TCN
Price: 8.7 USD
Availability: InStock

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Mouser No:

913-4C32M16D1A5TCN

Mfr. No:

AS4C32M16D1A-5TCN

Mfr.:

Alliance Memory

Description:

DRAM DDR1, 512Mb, 32M X 16, 2.5V, 66pin TSOP II, 200 MHz, Commercial Temp A

Datasheet:

AS4C32M16D1A-5TCN Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about Alliance Memory AS4C32M16D1A-5TCN

In Stock: 58

Stock:: 58

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On Order:: 216
Factory Lead Time:: 6

Weeks Estimated factory production time for quantities greater than shown.

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Unit Price:

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Ext. Price:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$8.70	$8.70
	$8.09	$80.90
	$7.83	$195.75
	$7.66	$383.00
	$7.48	$807.84
	$7.22	$1,559.52
	$7.04	$3,801.60
	$6.87	$7,419.60
2,592	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR
Memory Size:	512 Mbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	200 MHz
Package/Case:	TSOP-II-66
Organisation:	32 M x 16
Access Time:	700 ps
Supply Voltage - Min:	2.3 V
Supply Voltage - Max:	2.7 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Series:	AS4C32M16D1A
Packaging:	Tray
Brand:	Alliance Memory
Country of Assembly:	TW
Country of Diffusion:	TW
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	108
Subcategory:	Memory & Data Storage
Supply Current - Max:	90 mA
Unit Weight:	3.632 g

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Datasheet

AS4C32M16D1A-5TCN Datasheet (PDF)

REACH Declaration (PDF)

CNHTS:: 8542329010
USHTS:: 8542320028
JPHTS:: 854232021
KRHTS:: 8542321010
MXHTS:: 8542320201
ECCN:: EAR99

DDR1 Synchronous DRAM

Alliance Memory DDR1 Synchronous DRAM is a high-speed CMOS double data rate synchronous DRAM. It is internally configured with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK. Read and write accesses to the SDRAM are burst oriented. The Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.