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In Stock

RoHS

Mfr.	Mfr. No:	Qty	Ext Total

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AS4C4M32S-6BIN

Name: Alliance Memory AS4C4M32S-6BIN
Brand: Alliance Memory
SKU: 913-AS4C4M32S-6BIN
Price: 8.46 USD
Availability: InStock

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Mouser No:

913-AS4C4M32S-6BIN

Mfr. No:

AS4C4M32S-6BIN

Mfr.:

Alliance Memory

Description:

DRAM SDRAM, 128Mb, 4M x 32, 3.3V, 90-ball BGA, 166 MHz, Industrial Temp - Tray

Datasheet:

AS4C4M32S-6BIN Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Alliance Memory AS4C4M32S-6BIN

In Stock: 195

Stock:: 195 Can Dispatch Immediately

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Factory Lead Time:: 20 Weeks Estimated factory production time for quantities greater than shown.

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Unit Price:

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Ext. Price:

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Est. Tariff:

Pricing (USD)

Qty.	Unit Price	Ext. Price
	$8.46	$8.46
	$7.87	$78.70
	$7.62	$190.50
	$7.60	$380.00
	$7.29	$729.00
	$6.92	$1,314.80
	$6.81	$3,881.70
	$6.64	$7,569.60
2,660	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM
Memory Size:	128 Mbit
Data Bus Width:	32 bit
Maximum Clock Frequency:	166 MHz
Package/Case:	TFBGA-90
Organisation:	4 M x 32
Access Time:	5.4 ns
Supply Voltage - Min:	3 V
Supply Voltage - Max:	3.6 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Series:	AS4C4M32S
Packaging:	Tray
Brand:	Alliance Memory
Country of Assembly:	TW
Country of Diffusion:	TW
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	190
Subcategory:	Memory & Data Storage
Supply Current - Max:	160 mA

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Datasheet

AS4C4M32S-6BIN Datasheet (PDF)

REACH Declaration (PDF)

CNHTS:: 8542329010
CAHTS:: 8542320041
USHTS:: 8542320002
JPHTS:: 854232021
KRHTS:: 8542321020
MXHTS:: 8542320201
ECCN:: EAR99

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.