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In Stock

RoHS

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AS4C512M16D3LC-12BIN

Name: Alliance Memory AS4C512M16D3LC-12BIN
Brand: Alliance Memory
SKU: 913-C512M16D3LC12BIN
Price: 100.13 USD
Availability: InStock

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Mouser No:

913-C512M16D3LC12BIN

Mfr. No:

AS4C512M16D3LC-12BIN

Mfr.:

Alliance Memory

Description:

DRAM DDR3L, 8G, 512M X 16, 1.35V, 96-BALL FBGA, 800MHZ INDUSTRIAL TEMP C Die (MT41K512M16HA-125IT:A),

Datasheet:

AS4C512M16D3LC-12BIN Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about Alliance Memory AS4C512M16D3LC-12BIN

In Stock: 19

Stock:: 19 Can Dispatch Immediately

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Factory Lead Time:: 30 Weeks Estimated factory production time for quantities greater than shown.

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Ext. Price:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$100.13	$100.13
	$92.36	$923.60
	$89.32	$2,233.00
	$87.07	$4,353.50
	$84.87	$8,487.00

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR3L
Memory Size:	8 Gbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	800 MHz
Package/Case:	FBGA-96
Organisation:	512 M x 16
Access Time:	20 ns
Supply Voltage - Min:	1.283 V
Supply Voltage - Max:	1.45 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 95 C
Packaging:	Tray
Brand:	Alliance Memory
Country of Assembly:	TW
Country of Diffusion:	TW
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	190
Subcategory:	Memory & Data Storage
Supply Current - Max:	122 mA

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Datasheet

AS4C512M16D3LC-12BIN Datasheet (PDF)

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CNHTS:: 8542329010
CAHTS:: 8542320020
USHTS:: 8542320036
MXHTS:: 8542320299
ECCN:: EAR99

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.