IS43LR16320C-6BLI

ISSI
870-IS43LR16320C6BLI
IS43LR16320C-6BLI

Mfr.:

Description:
DRAM 512M, 1.8V, 166Mhz Mobile DDR SDRAM

Datasheet:
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Learn more about ISSI IS43LR16320C-6BLI

In Stock: 144

Stock:
144 Can Dispatch Immediately
Factory Lead Time:
16 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1   Maximum: 7
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:

Pricing (USD)

Qty. Unit Price
Ext. Price
$8.56 $8.56

Product Attribute Attribute Value Select Attribute
ISSI
Product Category: DRAM
RoHS:  
SDRAM Mobile - DDR
512 Mbit
16 bit
166 MHz
BGA-60
32 M x 16
6 ns
1.7 V
1.95 V
- 40 C
+ 85 C
IS43LR16320C
Tray
Brand: ISSI
Country of Assembly: Not Available
Country of Diffusion: TW
Country of Origin: CN
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 300
Subcategory: Memory & Data Storage
Supply Current - Max: 60 mA
Tradename: PowerSaver
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Attributes selected: 0

Datasheet

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CNHTS:
8542329010
USHTS:
8542320028
JPHTS:
854232021
MXHTS:
8542320201
ECCN:
EAR99

IS43LR16800F 2Mx16 Mobile DDR SDRAM

ISSI IS43LR16800F 2Mx16 Mobile DDR SDRAM is 134,217,728 bits Mobile Double Data Rate (DDR) Synchronous DRAM (SDRAM) organized as 4 banks of 2,097,152 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.

Mobile DDR SDRAM

ISSI Mobile DDR SDRAM is organized as 4 banks of 16,777,216 words x 16 bits and uses a double-data-rate architecture to achieve high-speed operation. The Data Input/Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. ISSI Mobile DDR SDRAM offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

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