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RoHS

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IM1G16D2DDBG-25I

Name: Intelligent Memory IM1G16D2DDBG-25I
Brand: Intelligent Memory
SKU: 822-IM1G16D2DDBG-25I
Price: 4.64 USD
Availability: OutOfStock

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Mouser No:

822-IM1G16D2DDBG-25I

Mfr. No:

IM1G16D2DDBG-25I

Mfr.:

Intelligent Memory

Description:

DRAM DDR2 1Gb, 1.8V, 64Mx16, 400MHz (800Mbps), -40C to +95C, FBGA-84

Datasheet:

IM1G16D2DDBG-25I Datasheet

ECAD Model:

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More Information

Learn more about Intelligent Memory IM1G16D2DDBG-25I

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Stock:: Non-Stocked

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Factory Lead Time:: 8 Weeks Estimated factory production time.

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$4.64	$4.64
	$4.33	$43.30
	$4.20	$105.00
	$4.10	$205.00
	$4.00	$400.00
	$3.84	$802.56
	$3.73	$1,559.14
	$3.66	$3,824.70

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Intelligent Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR2
Memory Size:	1 Gbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	400 MHz
Package/Case:	FBGA-84
Organisation:	64 M x 16
Access Time:	400 ps
Supply Voltage - Min:	1.7 V
Supply Voltage - Max:	1.9 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 95 C
Series:	IM1G16D2
Packaging:	Tray
Brand:	Intelligent Memory
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	209
Subcategory:	Memory & Data Storage
Supply Current - Max:	75 mA
Unit Weight:	192 mg

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Datasheet

IM1G16D2DDBG-25I Datasheet

CAHTS:: 8542320020
USHTS:: 8542320032
MXHTS:: 8542320299
ECCN:: EAR99

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

Double Data Rate 2 (DDR2) SDRAM

Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.