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In Stock

RoHS

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CD74AC164E

Name: Texas Instruments CD74AC164E
Brand: Texas Instruments
SKU: 595-CD74AC164E
Price: 0.8 USD
Availability: InStock

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Mouser No:

595-CD74AC164E

Mfr. No:

CD74AC164E

Mfr.:

Texas Instruments

Description:

Counter Shift Registers 8-Bit Srl-In Prl-Out

Datasheet:

CD74AC164E Datasheet

ECAD Model:

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More Information

Learn more about Texas Instruments CD74AC164E

In Stock: 800

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Factory Lead Time:: 6 Weeks Estimated factory production time for quantities greater than shown.

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Ext. Price:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$0.802	$0.80
	$0.801	$8.01
	$0.80	$20.00
	$0.77	$385.00
	$0.653	$653.00

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Counter Shift Registers
RoHS:
Counting Sequence:	Serial to Parallel
Number of Circuits:	1 Circuit
Number of Bits:	8 bit
Package/Case:	PDIP-14
Logic Family:	74AC
Logic Type:	CMOS
Number of Input Lines:	2
Propagation Delay Time:	157 ns, 17.5 ns, 12.5 ns
Supply Voltage - Min:	500 mV
Supply Voltage - Max:	6 V
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Tube
Brand:	Texas Instruments
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	MX
Function:	8 Bit Serial In Parallel Out
Mounting Style:	SMD/SMT
Number of Output Lines:	8
Operating Supply Voltage:	500 mV to 6 V
Product Type:	Counter Shift Registers
Series:	CD74AC164
Factory Pack Quantity:	25
Subcategory:	Logic ICs
Unit Weight:	1 g

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Datasheet

CD74AC164E Datasheet

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Mechanical Outline Drawing

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Product Catalogs

Logic Guide (Rev. AB)

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CNHTS:: 8542399000
CAHTS:: 8542390000
USHTS:: 8542390090
JPHTS:: 8542390990
TARIC:: 8542319000
MXHTS:: 8542310399
ECCN:: EAR99

CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers

Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers have two serial inputs (A and B) connected through an AND gate and an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either will set the input data line low. Data at A and B can be changed while CLK is high or low, provided the minimum set-up time requirements are met.