LMK5C33216ARGCTS1

Texas Instruments
595-LMK5C33216ARGCTS
LMK5C33216ARGCTS1

Mfr.:

Description:
Clock Synthesizer/Jitter Cleaner Three DPLL three AP LL two-input and 16

Datasheet:
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In Stock: 102

Stock:
102 Can Dispatch Immediately
Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 250)

Pricing (USD)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™ †
$58.80 $58.80
$48.57 $485.70
$46.01 $1,150.25
$44.06 $4,406.00
Full Reel (Order in multiples of 250)
$41.86 $10,465.00
1,000 Quote
† A MouseReel™ fee of $7.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable. ↩

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Clock Synthesizer/Jitter Cleaner
RoHS:  
16 Output
1.25 GHz
APLL
DPLL
VQFN-64
800 MHz
3.135 V
3.465 V
- 40 C
+ 105 C
LMK5C33216AS1
SMD/SMT
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: PH
Moisture Sensitive: Yes
Operating Supply Current: 1.205 A
Product: Network Synthesizers / Jitter Cleaners
Product Type: Clock Synthesizers / Jitter Cleaners
Factory Pack Quantity: 250
Subcategory: Clock & Timer ICs
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Attributes selected: 0

Datasheet

PCN

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CNHTS:
8542399000
USHTS:
8542390090
MXHTS:
8542399999
ECCN:
EAR99

LMK5C33216AS1 Network Synchronizer

Texas Instruments LMK5C33216AS1 Network Synchronizer is a network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications. The LMK5C33216AS1 is a device bundled with software support for IEEE-1588 PTP synchronization to a primary reference clock source. The network synchronizer integrates three DPLLs to provide jitter attenuation and hitless switching with programmable loop bandwidth and no external loop filters. This feature maximizes ease of use and flexibility. Each DPLL phase locks a paired APLL to a reference input.

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